Numerous electronic technologies such as digital computers, video equipment, and telephone systems have facilitated increased productivity and reduced costs in processing information in most areas of business, science, and entertainment. Testing the components is typically an important activity in ensuring proper performance and accurate results. The testing of semiconductor devices often involves performing test operations in accordance with controls referred to as test patterns. Execution of the test patterns typically involves loading and unloading scan chains with test vectors. However, there are a number of factors that can impact testing and traditional testing approaches are often costly and inefficient.
A system on chip (SoC) design is typically composed of several blocks of circuitry, some of which may have similar designs that are used or replicated in different parts of the chips. The several blocks of circuitry are often configured or organized in test blocks or test partitions for purposes of testing the circuitry. Traditional approaches to generating a full set of conventional test patterns targeted at multiple test partitions and executing the test patterns at substantially similar or parallel times is computationally intensive and time consuming. These conventional attempts are often unable to meet limited cost budgets and constrained project schedules.
Transistor feature sizes continue to shrink and smaller transistors allow more circuits to be included in a given die area. Although transistor technological advances offer a number of advantages, they also create design-for-testability (DFT) challenges. In traditional scan based tests, a significant portion of test time is spent loading and unloading test patterns or test vectors in the scan chains for application of test vectors. Larger and more complex circuits usually require longer test times. Conventional attempts at reducing test times by increasing shift clock frequencies or testing the entire design at the same time are often problematic and ineffective. Conventional test architectures are typically limited to supporting only one type of test vector across test partitions and don't typically enable parallel or true concurrent testing. For example, conventional solutions do not usually enable automatic test equipment and circuits under test to concurrently run a memory test in one test partition and scan test in another test partition. In a complex system-on-chip (SoC), interdependence of the clocking architecture across blocks and overall peak power consumption limits are typically major bottlenecks that hinder or prevent conventional independent parallel testing at a higher clock frequency.